The present invention pertains to apparatus for use in manufacturing integrated circuits and more particularly to apparatus and methods for detecting spot defects in such circuits.
Yield prediction and yield estimation are very important considerations in integrated circuit design and process development. Modeling of spot defect related yield losses have been investigated in order to improve yield prediction and estimation, and various yield models have been proposed as a result. However, most of these models assume that any spot defects on the surface of an integrated circuit die causes functional failure. Such an assumption is inaccurate and is especially misleading in the case of very large scale integrated (VLSI) circuits where spot defects observed on the surface of an integrated circuit do not necessarily cause functional failures.
For example, small defects may cause deformation of the circuit connectors when such defects occur in a congested region of the integrated circuit surface. However, they do not affect the performance of the circuit when they are located in other, less dense regions of the same integrated circuit. Thus, models that do not take into account realistic relationships between defect size and defect location, with respect to the detail of the integrated circuit layout, are faulty.
The need for a better characterization of the defect size in the yield analysis exists and models dealing with the distributed nature of defect size have been constructed. The accuracy of those models depends, however, on the accuracy of the information that describes the defect size distribution and defect density. Therefore, accurate identification of the defect size distribution and density are necessary factors for the accuracy of yield analyses that use such models.